The present invention relates to semiconductor devices, including integrated circuit (xe2x80x9cICxe2x80x9d) devices. More particularly, it relates to a methods and apparatus for planarizing and/or embossing patterns onto surfaces of semiconductor devices that contain silica dielectric coatings, and particularly nanoporous silica dielectric coatings, as well as to semiconductor devices produced by these methods and apparatus.
Processes used for the fabrication of semiconductor devices almost invariably produce surfaces which significantly deviate from a planar configuration. With the trend toward greater large scale integration, this problem is expected to increase. For instance, the production of integrated circuits typically requires multiple layers to be formed sequentially on a semiconductor substrate. Many of these layers are patterned by selective deposition or selective removal of particular regions of each such layer. It is well known that small deviations from the planar, condition in underlying layers become more pronounced with the addition of multiple additional layers of semiconductor and circuit features. Non-planar substrate surfaces can cause many problems that adversely impact the yield of finished products. For example, variations in interlevel dielectric thickness can result in failure to open vias, poor adhesion to underlying materials, step coverage, undesirable bends or turns in conductive metal layers, as well as xe2x80x9cdepth-of-focusxe2x80x9d problems for optical lithography.
In order to effectively fabricate multiple layers of interconnects it has become necessary to globally planarize the surface of certain layers during the multi-step process. Planarizing smoothes or levels the topography of microelectronic device layers in order to properly pattern the increasingly complex integrated circuits. IC features produced using optical or other lithographic techniques require regional and global dielectric planarization where the lithographic depth of focus is extremely limited, i.e., at 0.35 xcexcm and below. As used herein, the term xe2x80x9clocal planarizationxe2x80x9d refers to a condition wherein the film is planar or flat over a distance of 0 to about 5 linear micrometers. xe2x80x9cRegional planarizationxe2x80x9d refers to a condition wherein the film is planar or flat over a distance of about 5 to about 50 linear micrometers. xe2x80x9cGlobal planarizationxe2x80x9d refers to a condition wherein the film is planar or flat over a distance of about 50 to about 1000 linear micrometers. Without sufficient regional and global planarization, the lack of depth of focus will manifest itself as a limited lithographic processing window.
One previously employed method of planarization is the etch-back technique. In that process, a material, i.e., a planarizing material, is deposited on a surface in a manner adapted to form a surface relatively free of topography. If the device layer and the overlying material layer have approximately the same etch rate, etching proceeds through the planarizing material and into the device layer with the surface configuration of the planarizing layer being transferred to the device material surface. Although this technique has been adequate for some applications where a modest degree of planarity is required, present planarizng materials and present methods for depositing the planarizing material are often inadequate to furnish the necessary planar surface for demanding applications such as in submicron device fabrication.
The degree of planarization is defined as the difference between the depth of the topography on the device surface ht, and the vertical distance between a high point and a low point on the overlying material surface hd, divided by the depth of the topography on the device surface ht:             h      t        -          h      d            h    t  
The degree of planarization, in percent, is                     h        t            -              h        d                    h      t        xc3x97  100
Generally, for typical device configurations, planarization using the etch-back technique has not been better than approximately 55% as calculated by the method described above for features greater than 300 microns in width. The low degree planarization achieved by this technique is attributed to a lack of planarity in the planarizing material. Thus, for elongated gap-type features greater than 300 microns in width and 0.5 microns in depth, the usefulness of an etch-back technique has been limited.
U.S. Pat. No. 5,736,424, incorporated herein by reference in its entirety, describes a method for planarizing surfaces of substrates, such as semiconductor materials, by adding a pressing step to an etch-back process. In this reference, an optically flat surface is impressed on a curable viscous polymer coating on the substrate surface in need of planarization, followed by polymerization of the coating. The polymer is selected to etch at the same rate as the surface in need of planarization, and the polymer coating is etched down to the substrate, which is planarized by the process. While an improved planarization is claimed, apparently by starting the etch-back with a flatter surface, an added process step and complexity is required. In addition, this reference fails to provide a solution for planarizing substrates coated with nanoporous dielectric films, since by their nature, such low density films cannot be etched at the same rate as the underlying substrate.
Chemical mechanical polishing (CMP) is another known method that has been effectively used in the art to globally planarize the entire surface of dielectric layers. According to this method, a grainy chemical composition or slurry is applied to a polishing pad and is used to polish a surface until a desired degree of planarity is achieved. CMP can rapidly remove elevated topographical features without significantly thinning flat areas. However, CMP does require a high degree of process control to obtain the desired results.
Dielectric films formed of organic polymers, such as polyarylene ether and/or fluorinated polyarylene ether polymers, have been planarized by applying CMP to a partially cured film, followed by a final curing, as described in co-owned U.S. Ser. No. 09/023,415, filed on Feb. 13, 1998, the disclosure of which is incorporated by reference herein in its entirety. However, this reference fails to disclose how to planarize a silicon-based nanoporous dielectric material on the surface of a substrate.
Further, these previous methods are inadequate for providing localized planarization on different areas of a substrate surface, or for embossing other types of topography onto specific portions of a substrate surface. This is particularly important as the move towards ever larger integrated surface devices requires multiple planar surfaces, vias, trenches and the like, on disparate portions of a single substrate.
In addition, as IC feature sizes approach 0.25 xcexcm and below, problems with interconnect RC delay, power consumption and signal cross-talk have become increasingly difficult to resolve. The integration of low dielectric constant materials for interlevel dielectric (ILD) and intermetal dielectric (IMD) applications, is helping to solve these problems. One type of such low dielectric constant materials are nanoporous films prepared from silica, i.e., silicon-based materials. When air, with a dielectric constant of 1, is introduced into a suitable silica material having a nanometer-scale pore structure, dielectric films with relatively low dielectric constants (xe2x80x9ckxe2x80x9d), e.g., 3.8 or less, can be prepared on substrates, such as silicon wafers, suitable for fabricating integrated circuits.
There is also a need in the art to pattern the surfaces of potential microelectronic device s or integrated circuits. A number of such methods are known, and include photolithography, electron-beam lithography, and x-ray lithography. With electron-beam lithography, the beam is rastered across the surface of the article to produce the pattern. This is a slow, expensive process. Other previous methods for patterning include a method and apparatus for micro-contact printing that requires complex control mechanisms to keep the print head parallel with the dielectric surface, as disclosed, eg., by U.S. Pat. No. 5,947,027. Given the complexity of the apparatus and methods described by the ""027 patent, there remains a need in the art for a reliable and economic method of patterning on the surface of a dielectric film on a substrate.
For all of these reasons, there remains a need in the art for improved methods and apparatus for achieving the planarization and/or patterning of dielectric films, including silica-type dielectric films, on substrates. There is a particular need for such methods and apparatus for planarizing and/or embossing patterns onto nanoporous silica dielectric films.
In order to solve the above mentioned problems and to provide other improvements, the invention provides novel methods for effectively embossing planarized or patterned surfaces on polymer films. Films to be embossed by the methods and apparatus of the invention preferably include dielectric films suitable for use in microelectronic devices, such as integrated circuits. More preferably, the films to be treated are nanoporous silica dielectric films with a low dielectric constant (xe2x80x9ckxe2x80x9d), e.g., typically ranging from about 1.5 to about 3.8. The invention is also contemplated to include compositions produced by these methods. In one preferred embodiment, such compositions include films having surfaces that do not deviate from a planar topography by more than 0.35xcexc, and having a degree of planarization of at least 55%, or greater.
Nanoporous silica films can be fabricated by using a mixture of a solvent composition and a silicon-based dielectric precursor, e.g., a liquid material suitable for use as a spin-on-glass (xe2x80x9cSOGxe2x80x9d) material, which is deposited onto a wafer by conventional methods of spin-coating, dip-coating, etc., and/or by chemical vapor deposition and related methods, as mentioned in detail above. The silica precursor is polymerized by chemical and/or thermal methods until it forms a gel. Further processing by solvent exchange, heating, electron beam, ion beam, ultraviolet radiation, ionizing radiation and/or other similar methods that result in curing and hardening of the applied film.
At an appropriate point in the process, the applied film is contacted with a planarization object, also art-known as a compression tool. This is, for example, an object with a flat surface, or other type of surface suitable for the purpose. The planarization object and film are brought together with a force sufficient to effectively flatten the surface of the film, and thereafter the planarization object is separated from contact with the dielectric film, and any remaining process steps are conducted to produce a hardened nanoporous dielectric silica film. In certain optional embodiments, the gelling or aging step is skipped, and the planar surface or pattern is transferred to the dielectric film, and then heat cured, during or after contact with the working face of the planarization tool.
Apparatus for planarizing or patterning a dielectric film on a substrate broadly includes:
(a) a press for applying contact pressure to a planarization object, i.e., a compression tool,
(b) a compression tool having a working face that is planar or patterned, wherein said compression tool is operably connected to the press,
(c) a controller for regulating the position, timing and force applied to the dielectric film,
(d) a support for the substrate while said dielectric film is contacted by the compression tool.
The press for applying the compression tool can be any suitable art-known mechanical, hydraulic or gas-operated press device, for example, an arbor press, a hydraulic press, a pneumatic press, a moving cross-head press and variations and/or combinations thereof.
The support is any suitable device for fixing the substrate in place during the compression process, and optionally includes a workpiece holder, such as a vacuum chuck, or mechanical clamp(s) or other positioning devices, for maintaining the position and alignment of the substrate.
The compression tool is, i.e., a planarization object, and can be any suitable art-known device, for example, an optical flat, an object with a planar working surface, an object with a patterned working surface, a cylindrical object with a working surface that will emboss a dielectric film when said cylindrical object is rolled over said dielectric film, and combinations thereof Of course, such a compression tool has a working face that is capable of transferring a planar or patterned impression to the film to be impressed.
In a preferred embodiment, the compression tool is constructed to have at least one vent for transporting vapors or gases to or from the working face of the compression tool compression. For example, the vent preferably includes at least one opening on the working surface of the compression tool, so that the vent connects to a conduit through said compression tool for removing vapors or gases from the impressed film and/or for contacting the film with gas or vapor phase reagents during the impression step. When removing vapors or gases, the conduit connects to atmosphere or to a gas or vapor collection system. In one preferred variation, the conduit can be optionally connected to a source of pressurized gas or air, in order that a flow of gas can be directed to the working surface of the compression tool, to facilitate separation of the compression tool from the impressed film.
In a further preferred embodiment, the vent is a system that includes one or more purge inlets opening on the working face of the compression tool and passing completely through the compression tool, that operably connects to one or more purge channels running along the working face of said compression tool, that are operably connected to purge inlets. As for the vent and conduit described above, the purge inlets are optionally operably connected to a gas or vapor collection system and/or source of pressurized gas.
In another preferred embodiment, the support includes a compliant support that is formed using any suitable compliant material. Simply by way of example, such a compliant support can be formed from a compressible polymer, a compressible copolymer, a viscous material, a polymer bladder filled with a pressure regulated hydraulic fluid, and combinations thereof. The workpiece holder can optionally include a vacuum chuck for holding the substrate in a fixed position during compression.
The invention also includes a method of planarizing or patterning a dielectric film on a substrate that includes the steps of
(a) applying a dielectric film precursor to a substrate;
(b) planarizing or patterning said dielectric film in the apparatus of claim 1;
(c) gelling said dielectric film before, during or after step (b);
(d) curing the dielectric film.
The invention further includes a dielectric film on a substrate that is planarized or patterned by any of the above-described methods and/or apparatus. Further still, the invention includes a substantially planarized nanoporous dielectric silica coating on a substrate formed by a process comprising: applying a composition that comprises a silicon-based precursor onto a substrate to form a coating on said substrate, and conducting the following steps:
(a) optionally gelling or aging the applied coating,
(b) contacting the coating with a planarization object, i.e., a compression tool, with sufficient pressure to transfer an impression of the object to the coating,
(c) separating the planarized coating from the planarization object,
(d) curing the planarized coating;
wherein steps (a)-(d) are conducted in a sequence selected from the group consisting of
(a), (b), (c) and (d);
(a), (d), (b) and (c);
(b), (a), (d) and (c);
(b), (a), (c) and (d); and
(b), (c), (a) and (d).
It should be noted that when the above process is applied to a nanoporous silica dielectric film, step (b) is conducted with sufficient pressure to transfer an impression of the object to the coating, without substantially impairing formation of the nanometer-scale pores required to achieve a desirably low dielectric constant in the film.